PIC16C57C-04/SP【PDF 194/194 页】IC MCU OTP 2KX12 28DIP

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Sheet目录3872

190页 191页 192页 193页 [194页]

PIC18F2450/4450

2006 Microchip Technology Inc.

Advance Information

DS39760A-page 97

8.7

INTn Pin Interrupts

External interrupts on the RB0/AN12/INT0, RB1/AN10/

INT1and RB2/AN8/INT2/VMO pins are edge-triggered.

If the corresponding INTEDGx bit in the INTCON2

edge; if the bit is clear, the trigger is on the falling edge.

When a valid edge appears on the RBx/INTx pin, the

corresponding flag bit, INTxIF, is set. This interrupt can

be disabled by clearing the corresponding enable bit,

INTxIE. Flag bit, INTxIF, must be cleared in software in

the Interrupt Service Routine before re-enabling the

interrupt.

All external interrupts (INT0, INT1 and INT2) can wake-

up the processor from the power-managed modes if bit,

INTxIE, was set prior to going into the power-managed

modes. If the Global Interrupt Enable bit, GIE, is set, the

processor will branch to the interrupt vector following

wake-up.

Interrupt priority for INT1 and INT2 is determined by the

value contained in the interrupt priority bits, INT1IP

(INTCON3<6>) and INT2IP (INTCON3<7>). There is

no priority bit associated with INT0. It is always a high

priority interrupt source.

8.8

TMR0 Interrupt

In 8-bit mode (which is the default), an overflow in the

TMR0 register (FFh

→ 00h) will set flag bit, TMR0IF. In

16-bit mode, an overflow in the TMR0H:TMR0L

→ 0000h) will set TMR0IF. The

interrupt can be enabled/disabled by setting/clearing

enable bit, TMR0IE (INTCON<5>). Interrupt priority for

Timer0 is determined by the value contained in the

interrupt priority bit, TMR0IP (INTCON2<2>). See

Section 12.0 “Timer2 Module” for further details on

the Timer0 module.

8.9

PORTB Interrupt-on-Change

An input change on PORTB<7:4> sets flag bit, RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit, RBIE (INTCON<3>).

Interrupt priority for PORTB interrupt-on-change is

determined by the value contained in the interrupt

priority bit, RBIP (INTCON2<0>).

8.10

Context Saving During Interrupts

During interrupts, the return PC address is saved on

the stack. Additionally, the WREG, STATUS and BSR

registers are saved on the fast return stack. If a fast

return from interrupt is not used (see Section 5.3

“Data Memory Organization”), the user may need to

save the WREG, STATUS and BSR registers on entry

to the Interrupt Service Routine. Depending on the

user’s application, other registers may also need to be

saved. Example 8-1 saves and restores the WREG,

STATUS and BSR registers during an Interrupt Service

Routine.

EXAMPLE 8-1:

SAVING STATUS, WREG AND BSR REGISTERS IN RAM

MOVWF

W_TEMP

; W_TEMP is in virtual bank

MOVFF

STATUS, STATUS_TEMP

; STATUS_TEMP located anywhere

MOVFF

BSR, BSR_TEMP

; BSR_TMEP located anywhere

;

; USER ISR CODE

;

MOVFF

BSR_TEMP, BSR

; Restore BSR

MOVF

W_TEMP, W

; Restore WREG

MOVFF

STATUS_TEMP, STATUS

; Restore STATUS

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